1. Introduction to integrated circuits
1.1. Integrated circuits. Advantages and disadvantages in comparison with non-integrated circuits1.2. Integrated circuits design process. Abstraction levels.
2. VHDL language: fundamentals
2.2. Entities and architectures
2.2.1. Entity declaration
2.2.2. Architecture declaration2.2.3. Structural design and components instantiation
2.3.1. Concurrent and sequential sentences2.3.2. Sensitivity lists
2.4.3. Signals. Resolved signals. Resolution function2.4.4. Signals and variables assigment sentences
2.5. Data types
2.5.1. Scalar. Enumerated. Predefined enumerated types: BIT, BOOLEAN, STD_LOGIC. INTEGER. REAL. Physical types: TIME
2.5.2. ARRAY y RECORD
2.5.4. Operators. Conversion functions2.5.5. Predefined atributes. ARRAY atributes. Signal atributes: EVENT
3. Design of basic combinational and sequential circuits in VHDL
3.1. Conditional sentences and combinational circuits
3.1.1. IF_THEN_ELSE and conditional assignment: example with a 2:1 multiplexer.
3.1.2. CASE_IS_WHEN and selection assgnment: example with a 4:1 multiplexer.
3.1.3. Synthesis differences between IF and CASE.
3.1.4. Rules for processes that represent combinational circuits. Examples of bad operation.3.1.5. Other examples. Decoder. Comparator. Priority encoder.
3.2. Sequential circuits
3.2.1. Registers and flip-flops. Different versions with synchronous and asynchronous versions inputs.
3.2.2. Counters. Examples of counters: up-down and Johnson.
3.2.3. Finite state machines. Examples.3.2.4. Rules for processes that represent sequential circuits. Example of bad operation.
3.3. Design organization
3.3.1. Libraries. Predefined libraries. Use of libraries
3.3.2. Packages. Use of packages. Existing packages in the desing environments.
3.4. Iterative operations
3.5. Exam exercises
4. Design simulation in VHDL
4.1. Test bench structure.
4.2. Stimuli generation.
4.2.1. WAIT sentence. Examples.
4.2.2. Generation of a clock signal.4.2.3. Generation of waveforms.
4.3. Results checking
4.3.1. ASSERT sentences.
5. Manufacturing and packaging of integrated circuits
5.1. Review of MOS Technologies
5.1.1. MOS transistor equations. Body effect.
5.1.2. NMOS technology. NMOS inverter with different loads (resistive, enhancement NMOS and depletion NMOS). Elemental gates and main characteristics (delay and power consumption)
5.1.3. CMOS technology. The CMOS inverte: transfer characteristic. Transistors aspect ratio. Elemental gates and main characteristics (delay and power consumption). Pass transistor and transmission gate. Circuits with transmission gates (XOR and D flip-flop)
5.2. Main processes in integrated circuits manufacturing
5.2.1. Wafer preparation
5.2.3. Epitaxial growing, ionic implantation, diffusion
5.3. Manufacturing of a CMOS circuit
5.3.1. Manufacturing of a MOS transistor
5.3.2. Manufacturing of a CMOS inverter. Single and twin tub processes
5.4. Manufacturing of integrated passive components
5.4.1. Integrated resistors
5.4.2. Integrated capacitors
5.5. Packaging and mounting of integrated circuits
5.5.1. Functions of the packaging in ICs. Importance of the package
5.5.2. Package types
5.5.3. Multi-chip modules (MCM). MCM types
5.6. Aplication specific integrated circuits (ASICs). Types and characteristics
5.6.1. Digital, analog and mixed circuits
5.6.2. Custom and semi-custom circuits
5.6.3. Partially manufactured circuits (“Gate Array” and “Sea of gates”)
5.6.4. Partially pre-designed circuits, standard cells and macrocells
5.6.5. Full pre-manufactured circuits: programmable devices
6. Analysis and design of integrated circuits at physical level
6.1. Necessary masks for the manufacturing of a CMOS circuit
6.2. Design rules
6.2.1. Motivation of the design rules: manufacturing tolerances, etc.
6.2.2. The characteristic size parameter (lambda).
6.2.3. Design rules based on lambda.
6.2.4. Design rules checking (DRC)
6.3. Parameters extraction and simulation with PSPICE
6.4. Application examples
6.4.1. Logic gates and flip-flops
6.4.2. Circuits with transmission gates
6.4.3. Input and output elements (PADs)
6.4.4. Exam exercises
6.5. Practical considerations about the design
6.5.1. The latch-up effect. Reduction of latch-up risk. Effecto on the power supply distribution
6.5.2. Clock distribution
6.5.3. Delay optimization
7. Integrated circuits test
7.1.1. Fault model
7.1.2. Fault coverage
7.1.3. Test patterns generation
7.2. Design for testability (DFT)
7.2.1. Ad-hoc techniques
7.2.2. Structural techniques
18.104.22.168. Scan Path
22.214.171.124. Built-In Self-Test
7.2.3. Boundary Scan
8. Analysis and design of analog integrated circuits
8.1. Review of basic analog circuits with MOS transistors
8.1.1. Current sources
8.1.2. Common source NMOS amplifier
8.1.3. CMOS differential amplifiers
8.2. Design of CMOS amplifiers
8.2.1. Example: CMOS operational amplifier